Masterthesis: Side-Channel resistant Building Blocks for Post-quantum Cryptography on FPGAs

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Masterthesis: Side-Channel resistant Building Blocks for Post-quantum Cryptography on FPGAs

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Side-Channel resistant Building Blocks for Post-quantum Cryptography on FPGAs


Quantum mechanics was one of the most important achievements in the field of theoretical physics in the 20th century. In the 21st century, we expect as practical application of this theory the development of quantum computers. Quantum computers will be able to break important cryptographic primitives used in today’s digital communication. Therefore, there are ongoing activities aiming at the development, standardization, and application of post-quantum cryptography, i.e., cryptography that is able to defend against attacks by quantum computers.

Fraunhofer SIT investigates and implements post-quantum primitives targeting classical Internet applications, e.g., ecommerce and online banking in general and more specifically resource-restricted embedded hardware architectures used in, e.g., automotive systems and “Industry 4.0”. The goal of Fraunhofer SIT is to contribute to application oriented research and to support the transfer of academic research to industrial application.


Even if the cryptographic primitives and its building blocks are analytically secure, attacks on the concrete implementation might emit sensitive information about secret material during the execution. Implementation attacks are a very powerful approach in the field of cryptanalysis to reveal a secret key. One approach is side-channel analysis (SCA) which passively exploits side information like timing behavior or the power consumption and electro-magnetic emission profile when processing data on an integrated circuit. Compared to others, mounting side-channel analysis attacks is quite cheap and efficient. Therefore, this kind of attack poses a great threat in practice and it has become an important topic in academia and industry over the past two decades.

The efficiency of sorting both in software and in hardware is a well studied topic. However, if sorting is used as a building block for cryptographic primitives, security requirements need to be considered that have not been required before. The goal of this master thesis is the study of the side-channel vulnerability of a sorting hardware building block for efficient implementations of the Niederreiter cryptosystem using Goppa codes and to develop a constructive countermeasure on a Field Programmable Gate Array (FPGA). The cryptosystem is considered to be a mature and cryptographically secure candidate for post-quantum security if it can be implemented with resistance against side-channel analysis attacks.


- Read into side-channel analysis attacks.
- Get familiar with an existing FPGA implementation.
- Investigate the implementation for side-channel vulnerabilities.
- Develop and add a proper countermeasure.
- Evaluate the countermeasure.


- HDL programming (VHDL or Verilog),
- Python programming,
- and basic knowledge in electronics, cryptography, and statistics.


- Project files (zip, cleaned).
- Documentation and Thesis (pdf).
- Presentation slides (pdf).


For detailed information, please don’t hesitate to contact

Dr. Ruben Niederhagen
+49 6151 869-135

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