Masterthesis: Automated Tool for Securing Masked Hardware Implementation in the Presence of Glitches

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jwacker
Neuling
Neuling
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Registriert: 13. Mär 2018 11:14

Masterthesis: Automated Tool for Securing Masked Hardware Implementation in the Presence of Glitches

Beitrag von jwacker » 5. Jun 2018 10:41

Protecting hardware and software implementations against side-channel attacks is an
important challenge in cryptographic engineering. The masking countermeasure, introduced
in the seminal work of Ishai et al. in [3], is one of the most popular solutions for
this purpose. But while for software implementations masking is enough for guaranteeing
security, hardware implementations are inherently susceptible to physical leakages,
such as glitches, which can threaten the security. In order to deal with glitches, designers
usually insert registers in strategic positions of the circuit in order to "block" the
propagation of such leakages.

The main goal of the thesis is to present a method for automatizing the insertion of
registers in circuits, in order to keep an hardware implementation secure even in presence
of glitches.

See more information in the attached PDF and go to our Webpages under www.informatik.tu-darmstadt.de/cac
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thesis_proposal_registers.pdf
(125.62 KiB) 46-mal heruntergeladen
--
Jacqueline Wacker
Sekretariat Prof. Dr. Sebastian Faust
Technische Universität Darmstadt
FB Informatik/FG Angewandte Kryptographie
Mornewegstr. 30 (S4 14 | 3.2.07)
64293 Darmstadt

Tel. +49 6151 16-25716
Fax +49 6151 16-25717
jacqueline.wacker@crisp-da.de
www.informatik.tu-darmstadt.de/cac

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